Clock Jitter Estimation and Suppression in OFDM Systems Employing Bandpass Σ∆ ADC

In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture. A bandpass Σ∆ ADC is used for the analog to digital conversion process. An accurate and realistic model of the clock jitter in bandpass Σ∆ ADC is implemented. Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both phase and waveform noise. It is shown that for the case of sampling at IF stage, the effect of waveform noise is quite small and negligible compared to the phase noise effect. Therefore, an estimation and compensation method based on the existing phase noise compensation method is proposed for alleviating the effect of clock jitter. Simulation results are presented, showing the significant performance gain of our proposed algorithm, providing a new and innovative way of dealing with the clock jitter problem of bandpass A/D conversion in OFDM systems. Index Terms Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.